Job Description
*Participate in all phases of Physical Design of SoCs.
*Block level Physical design of complex Chip/IPs.
*STA & Timing Closure activities
*Work with Chip Integration team closely in Timing closure
*Complete the Block level/SoC Design including PDV
Salary:INR Best in the Industry
Industry: Semiconductors / Electronics
Functional Area: IT Software – Embedded , EDA , VLSI , ASIC , Chip Design
Role Category:Programming & Design
Role:Team Lead/Technical Lead
Keyskills
Hercules
Perl
Physical Verification
calibre
DFM
DRC
LVS
Physical design
STA
ICC Astro Encounter
CTS
Floorplan floorplanning pnr timing closure IR Drop
ECO
Netlist GDSII
Desired Candidate Profile
Education-
UG: B.Tech/B.E.
PG:Any Postgraduate
Doctorate:Any Doctorate – Any Specialization, Any Specialization, Doctorate Not Required
*Hands-on Experience with back-end tools (Floorplaning & PnR) preferably using ICC / Astro
*Clock Tree Synthesis
*Back-end design flows from Synthesis to Physical design verification
*Static Timing Analysis and Timing closure
*Power Analysis
Company Profile:
Newsoft Consultants Pvt. Ltd.
TOP Front-line MNC
TOP Front-Line MNC
View Contact Details:
Recruiter Name:Shashi Gupta
Contact Company:Newsoft Consultants Pvt Ltd
Email Address: [newsoft@nsoftindia.com , newsoft@nsoftindia.com]
Website:http://nsoftindia.com/index.php/hot-jobs/
Reference Id:PHYSICAL Design –