Macropace Technologies
3 – 7 yrs Malaysia
Job Description:
Design Verification:
Candidates should have 3+ yrs of Experience in OVM UVM< System Verilog.
They should have Minimum 1 Year exp on GLS or PCIE or SATA or USB Protocols
Salary:INR 6,50,000 – 9,00,000 P.A.
Industry:Semiconductors / Electronics
Functional Area:Engineering Design , R&D
Role Category:Engineering Design
Role:Design Engineer
Keyskills:
Design Verification OVM UVM SV System Verilog USB PCIE
Education-
UG: B.Tech/B.E. – Any Specialization, Electrical, Electronics/Telecommunication, Computers
Company Profile:
Macropace Technologies
Leading IT Recruitment firm
Recruiter Name:Poornima, poornima@macropace.com
Email Address:poornima@macropace.com