Intern-Technical

Candidates should possess B.E/B.Tech / M.Tech.

Candidates should have knowledge of Veriog/Systemverilog is must.

Knowledge of VHDL is a plus.

Sythesis, FPGA compilation knowledge/experience is a plus.

Scripting knowledge is an advantage (Shell, Perl, Sed, awk, tcl, etc.,)

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https://sjobs.brassring.com/1033/ASP/TG/cim_jobdetail.asp?jobId=1001840&PartnerId=25235&SiteId=5359