Digital Design Engineer

Job Description

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Location : Hyderabad

Position Title : Lead ASIC Digital Design Engineer

The Senior Verification Engineer will be a key member of the Synopsys Designware ARC Processor development team.Responsibilities include driving and applying state-of-the-art verification methodologies, creation and execution of Product Verification test plans, development of hardware verification test-benches and verification closure across Synopsys Designware ARC Processor IP. The candidate will work closely with the architects, design and verification teams locally and globally.

Typically requires a minimum of 8+ years of digital functional verification experience out of which at-least 3 years of experience should be in verifying processors or processors based designs.

Key responsibilities:

Responsibility for the creation and execution of Hardware IP Verification Plans relating to Synopsys Designware ARC Processor IP. He/She is expected to have a strong background (work or degree related) in Hardware Description language (HDL) design/verification, RISC processor architectures, and high-level hardware verification methodologies, e.g. coverage driven verification, OVM, UVM, VMM, eRM.During the hardware verification phase, he/she will be expected to work closely with the development teams globally and to sign-off on the testplan and execute upon its contents.

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Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: IT Software – Embedded , EDA , VLSI , ASIC , Chip Design
Role Category:Programming & Design
Role:Team Lead/Technical Lead

System Verilog
Formal Verification

Desired Candidate Profile
UG: Any Graduate – Any Specialization, Graduation Not Required
PG:Any Postgraduate – Any Specialization, Post Graduation Not Required
Doctorate:Any Doctorate – Any Specialization, Doctorate Not Required

Requirements (MUST):

B.Tech/B.E/B.Sc in Electronics domain as a minimum.
Hands-on experience of Hardware Verification Methodologies and best practices Coverage Driven Verification, constrained random testing using UVM/OVM/VMM/eRM
Understanding of Simulations, Emulation, Formal verification concepts
Has verified processors or processor based systems with bus/fabric based architectures. Knowledge of multicore architectures will be an added advantage
2-3 years of experience as a verification lead
HDL and Verification languages: SystemVerilog, Verilog, VHDL, Specman e, Vera; Other relevant languages: C, Perl, makefile generation, Shell scripting, SystemC
Tools: RTL Simulators, e.g. VCS, IES, Questa
Operating Systems: Linux, Windows
Written and Verbal skills:
* Ability to provide consultancy support, detailed status reporting and expert knowledge and advice to the ARC development teams during the verification phase of ARC Software and Hardware products
* Creation, modification and review of test documentation; plans, procedures, scenarios, data, test reports
* Ability to present verification results to the program management teams.
* Ability to describe problems in the defect tracking system

Analytical skills:
* Analysis of product testing requirements, e.g. required equipment and documentation required to close out on the product release cycle
* Ability to analysis test results and provision of reports

Required Personality Skills

Team player keen to work in a global development environment
Self motivated

Helpful qualifications:

Experience working within a global development team

Company Profile:
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in delivering semiconductor design software, intellectual property (IP), design for manufacturing (DFM) solutions and professional services that companies use to design systems-on-chips (SoCs) and electronic systems. The company?s products enable semiconductor, computer, communications, consumer electronics and other companies that develop electronic products to improve performance, increase productivity and achieve predictable success from systems to silicon.

Contact Details:
Recruiter Name:Sarni Tataverty
Contact Company:Synopsys
Email Address: []