As a Physical implementation engineer, you shall execute RTL to GDS flow. You shall be responsible for and own all aspects of physical design and physical verification efforts.
Position Requirements (Experience 3+ Yrs)
B.E,B.Tech,M.E,M.Tech,MS or equivalent degree with relevant experience.
Good understanding of static timing analysis (STA), EM/IR and sign-off flows.
Strong hands-on experience with –
1. Synthesis, Floor planning, power planning, placement, timing optimization, clock tree synthesis.
2. Timing convergence using high speed design techniques with signal integrity & EM/IR.
3. Run equivalence checks across gates-to-gates as design progresses.
4. Physical design verification.
EDA Tool Expertise: Encounter Digital Implementation System, PrimeTime-SI, StarXT, Calibre, Formality, Calibre.
Good scripting skills (perl, tcl).
Note: In case if you are not looking for better opportunity, Please refer your friends
Thanks & Regards,
Email Id:[email protected]
Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: IT Software – Embedded , EDA , VLSI , ASIC , Chip Design
Role Category:Programming & Design
Role:Team Lead/Technical Lead
static timing analysis
pnr p&r Netlist to GDS RTL to GDS Prime Time Gold Time
Desired Candidate Profile
UG: B.Tech/B.E. – Any Specialization
PG:M.Tech – Any Specialization
Doctorate:Any Doctorate – Any Specialization
Please refer to the Job description above
Physical Design Engineers
View Contact Details:
Recruiter Name:Sheshagiri Rao
Email Address: [[email protected]]